The present invention relates to a capacitor element having a three-dimensional structure and using a capacitor dielectric film made of a ferroelectric material or a high dielectric material.
To commercialize a RAM which enables high-speed wiring and reading at an unprecedentedly low voltage, vigorous research and development has been made on a ferroelectric material having a characteristic of spontaneous polarization or a high dielectric material. To implement a megabit-class semiconductor memory device to be mounted on an LSI composed of a CMOS with design rules of 0.18 μm or below, in particular, a capacitor element having a three-dimensional structure capable of providing a large capacitance with a small area should be developed. A capacitor element having a three-dimensional structure has such a configuration as termed a depressed, projecting, or cylindrical type and has an extremely large height compared with the width thereof.
Because a ferroelectric or high dielectric material is a metal oxide, it has the problems of easy reduction by hydrogen and consequent degradation of the electric characteristics thereof. To solve the problems, a technology which covers a capacitor element with a hydrogen barrier film capable of preventing the diffusion of hydrogen has recently begun being studied widely.
In view of the foregoing, it is essential for the commercialization of a capacitor element having a three-dimensional structure to develop an optimal structure covered with a hydrogen barrier film for the capacitor element. In this case, an important matter is to implement a structure capable of attaining the following objects derived from a large level difference which is peculiar to a three-dimensional structure.
The first object is to obtain a focus margin in a range achievable with the performance of a stepper in a lithographic step during wiring formation performed after the formation of a capacitor elements by minimizing the level difference even after the formation of a structure covered completely with hydrogen barrier films.
The second object is to obtain a focus margin in a range achievable with the performance of a stepper in a lithographic step performed to form a mask pattern for processing a hydrogen barrier film by minimizing the level difference in the step of forming the hydrogen barrier film covering the upper portion and sidewalls of the capacitor element.
A description will be given to conventional capacitor elements with reference to the drawings.
The description will be given first to a first conventional embodiment (see, e.g., Japanese Laid-Open Patent Publication No. H 11-135736 (paragraphs 0014 through 0021 at pages 4 and 5, FIG. 1 and paragraphs 0028 through 0035 at pages 5 and 6, FIG. 8)) with reference to FIG. 20.
FIG. 20 shows a principal-portion cross-sectional view of the capacitor element having a planar structure according to the first conventional embodiment.
As shown in FIG. 20, a semiconductor substrate 101 is formed with an isolation region 102 and an active region 103. A first interlayer insulating film 104 made of BPSG is formed to cover the semiconductor substrate 101. A first hydrogen barrier film 105 made of SiN is formed on the first interlayer insulating film 104. A capacitor element 109 composed of a lower electrode 106 made of Pt/Ti, a capacitor dielectric film 107 made of SrBi2Ta2O9 as a ferroelectric material, and an upper electrode 108 made of Pt which are formed successively in an upward direction is formed on the first hydrogen barrier film 105. The capacitor element 109 has an edge portion located inwardly of the edge portion of the first hydrogen barrier film 105.
A second hydrogen barrier film 110 made of TiN is disposed on the upper electrode 108. A third hydrogen barrier film 111 made of SiN and covering the capacitor element 109 is formed in contact relation with the first and second hydrogen barrier films 105 and 110. A second interlayer insulating film 112 made of SiO2 is formed on the first interlayer insulating film 104 to cover the capacitor element 109 enclosed by the first, second, and third hydrogen barrier films 105, 110, and 111.
A first contact hole 113 reaching the upper layer of the second hydrogen barrier film 110 is formed in the second interlayer insulating film 112 and the third hydrogen barrier film 111. A second contact hole 114 reaching the active region 103 is formed in the first and second interlayer insulating films 104 and 112. A wiring layer 115 for providing connection between the capacitor element 109 and the active region 103 via the first and second contact holes 113 and 114 is formed on the second interlayer insulating film 112.
When the capacitor element 109 has the planar structure which is extremely low in level, complete coverage of the capacitor element 109 with the first hydrogen barrier film 105 disposed in the layer underlying the capacitor element 109, the second hydrogen barrier film 110 disposed in the layer overlying the capacitor element 109, and the third hydrogen barrier film 111 disposed over the upper portion and sidewalls of the capacitor element can easily be realized in the first conventional embodiment. Accordingly, the reduction of the capacitor dielectric film 107 by hydrogen generated in a fabrication step after the formation of the capacitor element 109 can be prevented so that the degradation of the characteristics of the capacitor element 109 is suppressed.
The description will be given next to a second conventional embodiment (see, e.g., Japanese Laid-Open Patent Publication No. H11-135736 (paragraphs 0014 through 0021 at pages 4 and 5, FIG. 1 and paragraphs 0028 through 0035 at pages 5 and 6, FIG. 8)) with reference to FIG. 21.
FIG. 21 shows a principal-portion cross-sectional view of the capacitor element having a projecting three-dimensional structure according to the second conventional embodiment. The same reference numerals will be retained for the components shown in FIG. 21 which are used commonly in the first conventional embodiment.
As shown in FIG. 21, the semiconductor substrate 101 is formed with the isolation region 102 and the active region 103. The first interlayer insulating film 104 made of BPSG is formed to cover the semiconductor substrate 101. The first hydrogen barrier film 105 made of SiN is formed on the first interlayer insulating film 104. A plug 116 reaching the active region 103 is formed in the first hydrogen barrier film 105 and the first interlayer insulating film 104.
The second hydrogen barrier film 117 made of TiN or TaN is formed on the first hydrogen barrier film 105 to be in contact with the upper end of the plug 116. The lower electrode 106 made of Ru is formed on the second hydrogen barrier film 117. The capacitor dielectric film 107 made of (BaxSr1-x)TiO3 (0≦x≦1) as a high dielectric material is formed to cover the upper portion and sidewalls of the lower electrode 106 and the sidewalls of the second hydrogen barrier film 117. In addition, a third hydrogen barrier film 118 made of TiN is formed to cover the capacitor dielectric film 107 in contact relation with the first hydrogen barrier film 105. The third hydrogen barrier film 118 also functions as the upper electrode. The capacitor element 119 having the projecting three-dimensional structure composed of the lower electrode 106, the capacitor dielectric film 107, and the third hydrogen barrier film (upper electrode) 118 has thus been formed.
Although the capacitor element 119 having the three-dimensional structure with a large level difference is formed, the second conventional embodiment uses substantially the same hydrogen barrier structure as used in the case where the capacitor element 109 having the planar structure which is extremely low in level according to the first conventional embodiment is formed. Specifically, the capacitor element 119 is completely covered with the first and second hydrogen barrier films 105 and 117 disposed in the layers underlying the capacitor element 119 and with the third hydrogen barrier film 118 disposed over the upper portion of the capacitor element 119.
The description will be given next to a third conventional embodiment (see, e.g., Japanese Laid-Open Patent Publication No. 2000-286254 (paragraphs 0133 through 0139 at pages 15 and 16, FIG. 28)) with reference to FIG. 22.
FIG. 22 shows a principal-portion cross-sectional view of the capacitor element having a depressed three-dimensional configuration according to the third conventional embodiment. The depressed three-dimensional configuration has been mainstream in recent DRAMs. Since there is no statement of a hydrogen barrier film in the third conventional embodiment, the description will be given only to matters concerned with the capacitor element. The same reference numerals will be retained for the components shown in FIG. 22 which are used commonly in the first conventional embodiment.
As shown in FIG. 22, the semiconductor substrate 101 is formed with the isolation region 102 and the active regions 103. A first interlayer insulating film 120 made of SOG is formed to cover the semiconductor substrate 101. First plug 121 made of polysilicon and reaching the active regions 103 are formed in the first interlayer insulating film 120. A second interlayer insulating film 122 made of SOG is formed on the first interlayer insulating film 120. Second plugs 123 made of polysilicon and having lower ends thereof connected to the upper ends of the first plugs 121 are formed in the second interlayer insulating film 122. A third interlayer insulating film 124 made of SiN is formed on the second interlayer insulating film 122. A fourth interlayer insulating film 125 made of SiO2 is formed on the third interlayer insulating film 124.
Holes 126 for exposing the upper ends of the second plugs 123 are formed in the third and fourth interlayer insulating films 124 and 125. Since the lower electrodes 127 of the capacitor elements, which will be described later, are formed along the inner walls of the holes 126, the depth of each of the holes 126 should be maximized to increase the surface area of each of the lower electrodes 127 and increase the capacitance. This requires the fourth interlayer insulating film 125 formed with the holes 126 to have a thickness of about 1.3 μm.
The lower electrodes 127 made of polysilicon are formed on the inner walls of the holes 126. A capacitor dielectric film 128 made of Ta2O5 is formed over the respective surfaces of the lower electrodes 127 and the fourth interlayer insulating film 125. An upper electrode 129 made of TiN is formed on the upper surface of the capacitor dielectric film 128. Capacitor elements 130 each composed of the depressed three-dimensional structure composed of the lower electrode 127, the capacitor dielectric film 128, and the upper electrode 129 have thus been formed.
The description will be given next to the fourth conventional embodiment (see, e.g., U.S. Pat. No. 6,380,579 (line 55 in column 1 through line 55 in column 2 at page 11, FIG. 3)) with reference to FIG. 23.
FIG. 23 is a principal-portion cross-sectional view of the capacitor element having a cylindrical three-dimensional configuration according to the fourth conventional embodiment. The cylindrical three-dimensional configuration has been mainstream in recent DRAMs. Since there is no statement of a hydrogen barrier film in the fourth conventional embodiment, the description will be given only to matters concerned with the capacitor element. The same reference numerals will be retained for the components shown in FIG. 23 which are used commonly in the first conventional embodiment.
As shown in FIG. 23, the interlayer insulating film 104 made of SiO2 is formed on the semiconductor substrate 101. The plug 116 made of tungsten is formed in the interlayer insulating film 104. The lower electrode 106 serving as a storage node and having a cylindrical configuration is formed on the interlayer insulating film 104 to have a lower surface thereof in contact with the upper end of the plug 116. The lower electrode 106 is made of Pt or RuO2. The capacitor dielectric film 107 made of Ta2O5, (Ba1-xSrx)TiO3, or Pb(ZrxTi1-x)O3 (0≦x≦1) is formed over the respective surfaces of the lower electrode 106 and the interlayer insulating film 104. The upper electrode 108 serving as a plate electrode is formed on the surface of the capacitor dielectric film 107. The capacitor dielectric film 107 and the upper electrode 108 cover the bottom, upper, inner side, and outer side surfaces of the lower electrode 106. Since a capacitor element 131 thus composed of the cylindrical three-dimensional structure has a large surface area, it can provide a large capacitance.